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ATmega128
External Data Memory Timing
Table 137. External Data Memory Characteristics, 4.5 - 5.5 Volts, No W ait-state
8MHz Oscillator
Variable Oscillator
0
1
2
3a
3b
4
5
6
Symbol
1/t CLCL
t LHLL
t AVLL
t LLAX_ST
t LLAX_LD
t AVLLC
t AVRL
t AV W L
Parameter
Oscillator Frequency
ALE Pulse W idth
Address Valid A to ALE Low
Address Hold After ALE Low,
write access
Address Hold after ALE Low,
read access
Address Valid C to ALE Low
Address Valid to RD Low
Address Valid to W R Low
Min
115
57.5
5
5
57.5
115
115
Max
Min
0.0
1.0t CLCL -10
0.5t CLCL -5 (1)
5
5
0.5t CLCL -5 (1)
1.0t CLCL -10
1.0t CLCL -10
Max
16
Unit
MHz
7
8
t LL W L
t LLRL
ALE Low to W R Low
ALE Low to RD Low
47.5
47.5
67.5
67.5
0.5t CLCL -15 (2)
0.5t CLCL -15 (2)
0.5t CLCL +5 (2)
0.5t CLCL +5 (2)
ns
9
10
11
12
13
14
15
16
t DVRH
t RLDV
t RHDX
t RLRH
t DV W L
t W HDX
t DV W H
t W L W H
Data Setup to RD High
Read Low to Data Valid
Data Hold After RD High
RD Pulse W idth
Data Setup to W R Low
Data Hold After W R High
Data Valid to W R High
W R Pulse W idth
40
0
115
42.5
115
125
115
75
40
0
1.0t CLCL -10
0.5t CLCL -20 (1)
1.0t CLCL -10
1.0t CLCL
1.0t CLCL -10
1.0t CLCL -50
Notes:
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 138. External Data Memory Characteristics, 4.5 - 5.5V, 1 Cycle W ait-state
8MHz Oscillator
Variable Oscillator
0
10
12
15
16
Symbol
1/t CLCL
t RLDV
t RLRH
t DV W H
t W L W H
Parameter
Oscillator Frequency
Read Low to Data Valid
RD Pulse W idth
Data Valid to W R High
W R Pulse W idth
Min
240
240
240
Max
200
Min
0.0
2.0t CLCL -10
2.0t CLCL
2.0t CLCL -10
Max
16
2.0t CLCL -50
Unit
MHz
ns
328
2467X–AVR–06/11
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